1. Field of the Invention
This invention relates to an external bus controller. This invention is applied to, for example, system LSIs (large-scale integrated circuits), semiconductor chips comprising only an external bus controller, and similar.
2. Description of Related Art
In ordinary system LSIs, in addition to a CPU (central processing unit), internal memory and other integrated circuits, an external bus controller is provided. The CPU, internal memory, external bus controller, and other circuit blocks are interconnected using an internal bus. An internal bus is a bus provided within the system LSI, and comprises a data bus, address bus and control bus.
The external bus controller is connected to an external bus. An external bus is a bus used for interconnection of devices (semiconductor chips or other types of devices). An external bus comprises a data bus, address bus and control bus.
The data width of the data bus comprised by the external bus and the data width of a device need not be the same. For example, a 32-bit data bus can be connected to a 16-bit or an 8-bit device. When a 32-bit data bus is connected to a 32-bit device, all of the bits 0 to 31 of the data bus are connected to the device. However, when a 16-bit device is connected to a 32-bit data bus, the bits 0 to 15 of the data bus are connected to the device, and bits 16 to 31 are not connected to the device. And, when an 8-bit device is connected to a 32-bit data bus, the bits 0 to 7 of the data bus are connected to the device, and the bits 8 to 31 are not connected to the device.
When devices with a variety of data widths are connected to one external data bus, there is variation in the number of input/output terminals connected to each of the signal lines of the external data bus. For example, when an 8-bit device, a 16-bit device and a 32-bit device are connected to a 32-bit external data bus, bits 0 to 7 are connected to three devices, bits 8 to 15 are connected to two devices, and bits 16 to 32 are connected to only one device. Hence buts 0 to 7 are each connected to three terminals, bits 8 to 15 are connected to two terminals, and bits 16 to 32 are connected to only one terminal each.
Variation in the number of connected terminals gives rise to variation in the load capacitance of each of the signal lines. In general, the greater the number of connected terminals, the greater is the load capacitance. Further, variation in the load capacitance gives rise to variation in access times. This is because the larger the load capacitance, the longer the access time becomes. The operating frequency of the system LSI must be determined so as to accommodate the slowest access time. Hence variation in load capacitance impedes faster operation of the system LSI.
Moreover, in cases where for example devices are arranged on a printed circuit board (PCB), variations in the number of connected terminals complicates the wiring. This complexity increases the constraints imposed when laying out devices on the PCB.
In addition, when numerous input/output terminals are connected to a single signal line, signal reflections can no longer be neglected in some cases.